The present invention relates to a fine processing method of a semiconductor device, which is utilized, for example, to form a gate of a compound semiconductor device such as a MESFET (Metal Semiconductor Junction FET) and an HEMT (High Electron Mobility Transistor).
In the semiconductor devices such as a MESFET and an HEMT mainly used in a microwave band, a very short gate less than, e.g., 0.5 .mu.m is employed. To this end, such a fine resist pattern whose pattern width is below 0.5 .mu.m must be formed in the lithographic step. Since it is difficult in the normal photo exposing method to form such a fine resist pattern due to a limitation in the wavelength of the exposure light, the electron beam exposing method or the focus ion beam method has been conventionally employed.
However, there are problems in these conventional exposing methods that the lengthy exposure time is necessarily required and the productivities of the semiconductor device are deteriorated. Accordingly, a fine processing method capable of easily forming the fine pattern has been proposed (Japanese Patent Application No. Hei. 2-42857 filed by the same assignee of the present application and published on Nov. 1, 1991 under Japanese Patent Unexamined Publication No. Hei. 3-245527).
In this fine processing method, a resist pattern having a predetermined opening is formed on a substrate, a vapor deposited film is formed on a portion of the substrate which is exposed at the opening by performing an inclined vapor deposition on this resist pattern, and this vapor deposited film is used as a mask so as to execute an etching treatment.
In accordance with this fine processing method, the vapor deposition to the substrate which is exposed at the opening of the resist pattern, can be partially shielded by the resist pattern by selecting, for instance, the vapor deposition angle with regard to the resist pattern and the film thickness of the resist pattern when the inclined vapor deposition is carried out. As a result, since both the portion on which the vapor deposited film has been formed, and the portion on which no vapor deposited film is formed are fabricated on the substrate exposed at the opening of the resist pattern, the fine groove (pattern) is formed only on the portion on which no vapor deposited film is formed if the etching process is carried out.
Although the previously proposed fine processing method is a useful processing method capable of easily obtaining a pattern whose width is narrower than a width of another pattern obtained by the conventional photoexposure method, there are the following problems to be solved. These problems will now be explained with reference to FIGS. 6 and 7.
As represented in FIG. 6, a vapor deposition angle within a single wafer "W" is continuously varied according to positions on this wafer since metal particles to form a vapor deposited film are emitted from a vapor deposition source "P" in a radial form. For instance, the vapor deposition angle is continuously changed from 3.degree.-5.degree.-7.degree. over one end of the wafer W, a central part thereof, and the other end thereof.
As shown in FIG. 7, since the vapor deposition angle is changed within the wafer "W", widths of the exposed region 4 of the substrate from the edge portion of the resist pattern 2 formed on the substrate 1 to the edge portion of the vapor deposited film 3 on the substrate 1, are varied in accordance with the vapor deposition angles. For example, in case of the resist pattern 2 having the width of 1.5 .mu.m, the widths of the exposed region 4 are varied as follows. If the vapor deposition angle is 3.degree., then the width of the exposed region 4 of the substrate is 0.079 .mu.m. If the vapor deposition angle is 5.degree., then the width of this exposed region 4 is 0.131 .mu.m. If the vapor deposition angle is 7.degree., then the width of this exposed region 4 is 0.184 .mu.m.
Such a variation in the widths of the exposed region 4 of the substrate appears as a variation in a gate length. As a consequence, according to the previously proposed fine processing method, since the gate length is varied due to the continuous variation in the vapor deposition angle within the same wafer, there is a problem that fluctuation exists in the performance of the semiconductor device.